Z80 CPU architecture

Z80 CPU architecture

The Z80 CPU is an 8-bits processor witch was constructed in the beginning of July 1976, with ideas from Intel 8080. That was before the Intel-Company started, and made a better 8080-processor, with backward compatibility and with a lot of new instructions.

The interesting thing about the Z80-CPU is that you can all ready see the beginning to: what was about to become pipelined constructions. The Z80 CPU became fast a very popular Processor for small systems - especially later when the processor fall in prize. Now a Z80-processor costs about a dollar, and many are using it of tradition, witch make it even more popular, if you look at the homepage of Zilog, then you will see that today there is a lot of new variants of chips for Z80 systems, used in a wide range of applications.

Processor architecture:

The Z80 CPU has a very interesting architecture. First of all it has 'fetch/execute overlapping', witch means that it's possible to get (fetch) next instruction from memory while the first instruction are executed. This system is also used in the Intel 8080, and other processors from that time. Another thing that is typical from that time is that those processors areCISC-processors, and that they have variable instructions length. The Z80 CPU instructions-length can be from one to four bytes long. To increase the Z80 CPU speed most instructions are only one byte long. 252 instructions are one byte, the rest are 2, 3 or 4 bytes long.

Fig 1. Fetch/execute overlap.

Another aspect in processor- architecture are the number of internal registers, and if they are dedicated to special purposes. The Z80 CPU internal organization is made visible on the figure below:

Fig 2. Z80 CPU internal organization.

It shows on the figure: 20 - 8-bits registers, and 4 - 16-bits registers. The four 16-bits registers are: PC (Program Counter), SP (Stack Pointer) and the two Index-registers, IX and IY.

The 20 - 8-bit registers are grouped into two banks with 10 registers. 8 witch can be used together as 4 - 16-bit register-pairs, an 8-bit accumulator and a 8-bit flag-register. The Accumulator A, are used for all calculations. The F-register (flags) are used to determine if the result is positive, negative, zero etc

The Register-pairs BC and DE are mostly used for counters and storage of part-results. The Register-pair HL can be used in a wide range of instructions mostly as addressing (pointing to memory). The forgotten registers W and Z are only used for internal operations in the processor, like jump to new addresses. (The CPU can only transfer 8 bits at a time, so to transfer (load) a 16-bit address, it will first store it in WZ) .

The registers B, C, D, E, F, H, L, W and Z can be changed very fast with B', C', D', E', F', H', L', W' and Z', with the instruction EXX. For this purpose a MUX is used, witch is the fastest way to change the value in 9 registers with 9 others. The A and F are switched with A' and F' with the instruction EX AF,AF'. This finesse are mostly used with interrupt routines, so that the main program are using the main set of registers and the interrupt routine are using the EXX registers, this speeds up the interrupt routine, which can be important in embedded applications.

The Z80 CPU has with Intel, inspired to the global processor development and are still alive today more than 20 years after it's construction and it seems like it will continue to live many years more.

Info source: Programming the Z80 by Rodney Zaks. From SYBEX (ISBN: 0-89588-094-6)

Microcomputer systems are extremely simple to construct using the Z-80 components. Any such system consists of tree parts:

1. Z80 CPU (Centrel Processing Unit)

2. Memory (ROM and RAM)

3. Interface circuits to peripheral devices

The CPU is the heart of the system. Its function is to obtain instructions from the memory and perform the desired operations. The memory is used to contain instructions and in most cases data that is to be processed. For example, a typical instruction sequence may be to read data from a specific peripheral device, store it in a location in memory, check the parity and write it out to another peripheral device. Note that the Zilog component set includes the CPU and various general purpose I/O device controllers, while a wide range of memory devices may be used from any source. Thus, all required components can be connected together in a very simple manner with virtually no external logic. The user's effort then becomes primarily one of software development. That is, the user can concentrate on describing his problem and translating it into a series of instructions that can bo loaded into a microcomputer memory. Zilog is dedicated to making this step of software generation as simple as possible. A good example of this is our assembly language in which a simple mnemonic is used to represent every instruction that the CPU can perform. This language is self documenting in such way that from the mnemonic the user can understand exactly what the instruction is doing without constantly checking back to a complex cross listing.

DESCRIPTION

The Z80 microprocessor is an 8 bit CPU with a 16 bit address bus capable of direct access of 64k of memory space. It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, acceses an additional 308 instructions. The Z80 was modeled after the 8080 and contains the 78 - 8080 opcodes as a subset to it's language.

Programming features include an accumulator and six eight bit registers that can be paired as 3-16 bit registers. In addition to the general registers, a stack-pointer, program-counter, and two index (memory pointers) registers are provided. While not in the same leauge as the 80486 or 68000 series, the Z80 is extremely useful for low cost control applications. One of the more useful features of the Z80 is the built-in refresh circuitry for ease of design with DRAMs.

The Z80 comes in a 40 pin DIP package. And resently also in a 44 pin SMD and QFP. It has been manufactured in A, B, and C models, differing only in maximum clock speed. It also has been manufactured as a stand-alone microcontroler with various configurations of on-chip RAM and EPROM.

Z80 CPU Pin Description:

_________ _________
_| __/ |_
<-- A11 |_|1 40|_| A10 -->
_| |_
<-- A12 |_|2 39|_| A9 -->
_| |_
<-- A13 |_|3 Z80 CPU 38|_| A8 -->
_| |_
<-- A14 |_|4 37|_| A7 -->
_| |_
<-- A15 |_|5 36|_| A6 -->
_| |_
--> CLK |_|6 35|_| A5 -->
_| |_
<--> D4 |_|7 34|_| A4 -->
_| |_
<--> D3 |_|8 33|_| A3 -->
_| |_
<--> D5 |_|9 32|_| A2 -->
_| |_
<--> D6 |_|10 31|_| A1 -->
_| |_
VCC |_|11 30|_| A0 -->
_| |_
<--> D2 |_|12 29|_| GND
_| |_
<--> D7 |_|13 28|_| /RFSH -->
_| |_
<--> D0 |_|14 27|_| /M1 -->
_| |_
<--> D1 |_|15 26|_| /RESET <--
_| |_
--> /INT |_|16 25|_| /BUSRQ <--
_| |_
--> /NMI |_|17 24|_| /WAIT <--
_| |_
<-- /HALT |_|18 23|_| /BUSAK -->
_| |_
<-- /MREQ |_|19 22|_| /WR -->
_| |_
<-- /IORQ |_|20 21|_| /RD -->
|_____ _______ ______ _______|

Z80 CPU SMD and QFP Pin Description:

A lot of people have been requesting the Z80 pinouts. Well, here they are,
directly from the Zilog Z80 Microprocessor Family Databook.

44 pin QFP:

1 - CLK 2 - D4 3 - D3 4 - D5 5 - D6
6 - +5V 7 - D2 8 - D7 9 - D0 10 - D1
11 - NC 12 - ~INT 13 - ~NMI 14 - ~HALT 15 - ~MREQ
16 - ~IORQ 17 - NC 18 - ~RD 19 - ~WR 20 - ~BUSACK
21 - ~WAIT 22 - ~BUSREQ 23 - ~RESET 24 - ~M1 25 - ~RFSH
26 - GND 27 - A0 28 - A1 29 - A2 30 - A3
31 - A4 32 - A5 33 - NC 34 - A6 35 - A7
36 - A8 37 - A9 38 - A10 39 - NC 40 - A11
41 - A12 42 - A13 43 - A14 44 - A15


The '~' stands for 'not' ( i.e. active low ). The pins are counted
counter-clockwise, pin 1 starting from the bevel ( or the corner dot ).
This may be different on the Toshiba chip used in the TI so I assume no
responsibility for anyone frying their calc.

Z80 PIO Pin Description

_________ _________
_| __/ |_
<--> D2 |_|1 40|_| D3 <-->
_| |_
<--> D7 |_|2 39|_| D4 <-->
_| |_
<--> D6 |_|3 Z80 PIO 38|_| D5 <-->
_| |_
--> /CE |_|4 37|_| /M1 <--
_| |_
--> C/D |_|5 36|_| /IORQ <--
_| |_
--> B/A |_|6 35|_| /RD <--
_| |_
<--> PA7 |_|7 34|_| PB7 <-->
_| |_
<--> PA6 |_|8 33|_| PB6 <-->
_| |_
<--> PA5 |_|9 32|_| PB5 <-->
_| |_
<--> PA4 |_|10 31|_| PB4 <-->
_| |_
GND |_|11 30|_| PB3 <-->
_| |_
<--> PA3 |_|12 29|_| PB2 <-->
_| |_
<--> PA2 |_|13 28|_| PB1 <-->
_| |_
<--> PA1 |_|14 27|_| PB0 <-->
_| |_
<--> PA0 |_|15 26|_| VCC +5V
_| |_
--> /AOE |_|16 25|_| CLOCK <--
_| |_
--> /BOE |_|17 24|_| INT ENABLE IN <--
_| |_
<-- AREADY |_|18 23|_| /INT -->
_| |_
<-- D0 |_|19 22|_| INT ENABLE OUT -->
_| |_
<-- D1 |_|20 21|_| BREADY -->
|_____ _______ ______ _______|

C/D CONTROL=1, DATA=0
B/A PORT B=1, PORT A=0
Z80 5seconds Timer for 10MHz




MAIN: CALL TIMER5



TIMER5: LD E,35H
J60: LD B,0FFH
J61: LD D,0FFH
J62: DEC D
JP NZ,J62
DEC B
JP NZ,J61
DEC E
JP NZ,J60
RET

---

Z80 multivibrator

Point: Use Loop Output 00H and FFH at 1 second interval.

ORG 0000H
LD SP,0FFFFH

PPI1 EQU 37H
PORTB1 EQU 35H

LD A,90H
OUT (PPI1),A

LOOP: LD A,0
OUT (PORTB1),A
CALL TIMER1
LD A,0FFH
OUT (PORTB1),A
CALL TIMER1
JP LOOP

TIMER1: LD E,0AH
J50: LD B,0FFH
J51: LD D,0FFH
J52: DEC D
JP NZ,J52
DEC B
JP NZ,J51
DEC E
JP NZ,J50
RET

END

Anexa 4

Transferuri pe 8 biti
Transferuri pe 16 biti
Schimburi intre registre, transfer de blocuri, cautari
Operatii aritmetice si logice pe 8 biti
Operatii aritmetice generale si operatii de comanda
Operatii aritmetice pe 16 biti
Prelucrari pe bit
Salturi
Apeluri de subrutine, reveniri, instructiuni de restart
Operatii de intrare/ iesire

Transferuri pe 8 biti

Transferuri pe 16 biti

Schimburi intre registre, transfer de blocuri, cautari

Operatii aritmetice si logice pe 8 biti

Operatii aritmetice generale si operatii de comanda

Operatii aritmetice pe 16 biti

Operatii aritmetice pe 16 biti

Prelucrari pe bit

Salturi

Apeluri de subrutine, reveniri, instructiuni de restart

Operatii de intrare/ iesire